1. Field of the Present Invention
The invention is in the field of integrated circuit testing and, more specifically, characterizing the delay associated with critical paths in an integrated circuit.
2. History of Related Art
Scaling trends in the semiconductor industry have resulted in a doubling of integrated circuit operating frequencies every two years. Scaling trends have also led to smaller dimensions causing the number of transistors on a chip to double every two years. In contrast, die sizes have only increased by approximately 14% every year. As a result, integrated circuits are much denser in terms of the percentage of the die size area that is populated by a transistor or other device. This increased density has severely limited manufacturing controllability as well as the ability to observe and characterize the integrated circuit. As a result, the testing, debugging, and diagnosing of modern integrated circuits is extremely challenging. Nevertheless, there is a clear necessity to characterize the post-silicon electrical behavior of integrated circuits because design models and simulation packages cannot fully account for the variability that is introduced by the manufacturing process.
Referring to FIG. 1, a conceptual illustration of a fundamental test or characterization problem is shown. In FIG. 1, an integrated circuit 100 is represented as having two basic types of elements, namely, state-holding elements or latches 102-1 and 102-2 (collectively or generically referred to herein as latch(es) 102) and combinational logic elements 104-1 and 104-2 (generically or collectively referred to herein as combinational logic 104). The latches 102 depicted in FIG. 1 may represent multiple latches (not shown individually) and may be more accurately referred to as latch stage(s) 102.
The latches in a latch stage 102 are driven by a system clock 106. The value at the output of a latch following an active transition of the system clock 106 reflects the value at an input of the latch when the clock transitioned. Once the output achieves a steady state following the system clock transition, the output value is static until the next active transition of the system clock.
The combinational logic elements 104 represent logic functions such as logical AND, NAND, OR, NOR, and EXOR gates as well as logical inverters. The amount of combinational logic that may be placed between a pair of latching stages 102 is limited. More specifically, combinational logic, as is the case for all real circuits, exhibits signal delay. A signal transition (represented by reference numeral 108) at the input to combinational logic 104 requires a finite amount of time to produce a signal transition (109) at the output of combinational logic 104. Thus, there is a delay between transition 108 and transition 109 and this delay is a characteristic of the circuit path from the input signal to the output signal.
Meanwhile, system clock 106 is oscillating at a predetermined frequency. System clock 106 includes a first transition 118 that clocks the transition 108 at the input to combinational logic 104-1. If the amount of time between system clock transition 118 and the next active transition 119 of clock signal 106 is less than the amount of delay between transitions 108 and 109, transition 109 will not occur until after the clock transition 119. This condition is referred to as a delay fault because the excessive delay in combinational logic 104-1 causes a fault when transition 109 does not get latched through latch stage 102-2.
It would be highly desirable to implement a technique to measure the post-silicon delay between transition 108 and 109 for one or more critical paths. It would be further desirable if the implemented solution did not require significant die area and did not require a significant modification in testing equipment.